The current communication nodes able to perform circuit switching functions between synchronous link interfaces such as channelized time division multiplex on primary access links have an internal timing clock which is synchronized with the clock of one of the synchronous link interfaces. This prevents synchronous interfaces belonging to different Carriers not synchronized between them from being interconnected.
In such an environment, the internal timing clock of the node is synchronized with the timing clock of one Carrier by means of a phase locked loop, so that the circuit switching functions can be performed between interfaces belonging to this Carrier without any slippage.
However, since the node internal timing clock cannot be synchronized with the timing clocks of the other Carriers, the circuit switching functions between the interfaces belonging to these Carriers cannot be performed without any slippage, which is a major drawback.
In addition, the implementation of the Phase Locked Loop in charge of the synchronization of the internal timing clock of the node with the clock of one of the Carriers is complex and difficult to implement at high speed.